High speed digital systems, such as engineering workstations and personal computers, require clock sources to provide a timing reference. It is imperative that these timing references be highly accurate and stable. Otherwise, the performance of the digital systems relying on these clock sources would be impaired. One method for achieving a clean, fast, and accurate clock source is to use a crystal oscillator coupled with a phase-lock-loop (PLL) circuit to regulate its frequency. In this type of arrangement, the goal then is to design the PLL such that it exhibits low jitter and high bandwidth in order to generate an optimal clock signal.
The PLL circuitry in the clock generator typically contains a voltage controlled oscillator (VCO) that receives a voltage level maintained by filter components. Normally, charging currents and voltage controlled oscillator gains are so high that externally situated filter components are required to achieve the low jitter and bandwidth requirements necessary for clock generator circuits. However, external, "off-chip," filter components (e.g., capacitors, etc.) increase the overall cost of the digital system in part by making manufacturing more complex, and also increase the physical size of the digital system. Furthermore, off-chip filter components also decrease system reliability by increasing the phase jitter because they are susceptible to external noise being injected into the clock circuit. Clock jitter is reduced if the traditional external elements of the PLL loop filter can somehow be fabricated onto the chip itself. However, in order to integrate filter components "on-chip," it is mandatory to use smaller sized filter components. Using the standard sized filter components is impractical because it would consume too much of the silicon area of the chip. In other words, the chip is not big enough to fit all the traditional filter components within it. Thus, one must resort to using smaller sized filter component to achieve the same PLL characteristics. But this leads to tighter filter requirements because smaller sized filter components are extremely sensitive to fluctuations in voltage and current levels. Even the smallest amount of voltage and/or current fluctuation can significantly worsen the PLL's jitter and bandwidth characteristics. One factor contributing to worsening the jitter is the Rcb leakage current inherent with any transistor.
Accordingly, what is needed is some method for minimizing the jitter and maintaining the bandwidth of an on-chip PLL. The present invention provides a unique, novel solution by implementing a circuit which detects the amount of leakage current associated with the Rcb path of a high side current source transistor of the PLL and automatically injects an equal but opposite amount of current back to the filter components, such that the net effect is as if there was no leakage at all. Thus, the present invention enables the PLL to be integrated on the same chip, which reduces cost and minimizes its susceptibility to external noise and other interferences, while also minimizing the effects of current leakage thereby reducing clock jitter and maintaining tight PLL bandwidth requirements.